Semiconductor integrated circuit devices, such as dynamic RAMs, with screen partitioned type structural elements in the memory cell section, for example, stacked cell capacitors formed with a cylindrical shape for increasing the capacity, can be manufactured by conventional processes such as those shown in FIGS. 28-33.
In this memory cell section, as shown in FIG. 28, the element region is provided by a field SiO.sub.2 film 2 that is formed on top of the p.sup.- -type silicon substrate 1 by the LOCOS (local oxidation of silicon) method, a gate oxide film 5 is formed in this element region, and on top of this, a polysilicon word line WL and an SiO.sub.2 insulating layer 6, which are provided on the side wall 60 of the silicon nitride, are formed by CVD (chemical vapor deposition), and the n.sup.+ -type semiconductor regions 3 (source region) and 4 (drain region) are formed using a self-aligning system using this word line WL as the mask.
A contact hole 49 that reaches the n.sup.+ -type drain region 4 is provided in this insulating layer 6, and bit line BL is adhered and formed. The upper surface of the bit line BL is protected by insulating layer 61, and side wall 62 is provided on its side surface. Contact hole 10 is formed in a portion of the insulating layers 6 and 70 on top of source region 3, and the polysilicon layer 11, which forms a portion of the lower electrode (storage node) of the capacitor, is deposited by CVD so as to include this contact hole 10 and connect to source region 3.
An oxide insulating film 71 made of a phosphosilicate glass that acts as a support pillar (or is used as a spacer that regulates the shape of the polysilicon lower electrode) when forming the cylindrical (crown-shaped) polysilicon lower electrode for the cylindrical stacked cell capacitor, which will be presented below, is formed by CVD on top of this polysilicon layer 11, and a photoresist mask 72 is then formed in the prescribed pattern for etching this insulating layer 71 to the shape of the spacer.
Then, as shown in FIG. 29, insulating layer 71 is dry etched using the mask 72, and the silicate glass layer 71 directly beneath the unmasked region 73 is selectively removed. As an etching gas for this dry etching, a mixed gas of CF.sub.4, CHF.sub.3, and Ar (CF.sub.4 /CHF.sub.3 /Ar) is used, but as is illustrated, etching perpendicularly is very difficult, and it can be etched in the shape of an inverted frustum with a slanted surface 74.
When the insulating layer surface region beneath the unmasked region 73 in FIG. 29 is etched, the accumulated substances 75 from the etching gas (particularly that generated from CHF.sub.3) adheres on the top of the slanted surface, so the slanted surface is completely covered before the etching is done in the perpendicular direction. This type of condition successively creates a virtual line in the thickness direction of insulating layer 71 and is thought to occur because of the mask operation in relation to the dry etching. The accumulated substance 75 is generated on the side surfaces of the insulating layer 71 that remain in the shape of a spacer with the dry etching, but in the following figures, the illustrations are omitted for the purpose of simplification.
Next, as shown in FIG. 30, after forming the polysilicon layer 76, which becomes the lower electrode of the capacitor, over the entire surface by CVD, as shown in FIG. 31, the polysilicon layer 76 is uniformly etched from the position of the broken line, the polysilicon layer 11 of the foundation is also further etched, and the polysilicon layer 76 is left on the side surface of spacer material 71. In this etching, a mixed gas of Cl.sub.2 and O.sub.2 (Cl.sub.2 /O.sub.2), which has superior isotropic properties, is used, but as mentioned above, because the side surface of spacer 71 has a slanted surface, at the same time as etching gas is operating (this is, perpendicular to substrate 1) in a direction perpendicular to the substrate in the polysilicon layer 76 on top of the slanted surface, etching is also done in the thickness direction of the polysilicon layer 76.
As a result, as shown in FIG. 31, on the side surface of spacer material 71, the thickness of the polysilicon layer 76, which should be left in the thickness of the shaded area, becomes thin. Since, in this way, the electrical resistance of the lower electrode of the capacitor increases, it is undesirable.
The spacer material 71 supported by the side surface of polysilicon layer 76, as shown in FIG. 32, is removed by dry etching, which uses CF.sub.4 /CHF.sub.3 /Ar as an etching gas, or by wet etching, and forms the cylindrical polysilicon lower electrode 76, with a cross section in the shape of a frustum that is connected to the n.sup.+ -type region 3 of substrate 1.
Following that, as shown in FIG. 33, high dielectric film 77 made of polysilicon nitride and capacitor upper electrode (plate electrode) 78 made of polysilicon are deposited over the entire surface by CVD, and memory cell MC' is made with a COB (cell over bit line) construction having a number of stacked cell capacitors CAP' that are separated from each other.
In this type of conventional manufacturing process, as presented above, because the same side surfaces of the spacer material 71 become slanted surfaces due to the patterning of the spacer material 71, particularly as shown in FIG. 29, after the etching of the polysilicon layer 76 shown in FIG. 31, its thickness is easily reduced, causing deterioration in the performance of the electrode.
Thus, to circumvent this problem, as shown in FIG. 34, making the thickness of the polysilicon layer 76 large has been considered, and the side surfaces of the spacer material 71 remain sufficiently thick even by the etching shown in FIG. 35.
However, with this, since the thickness of the polysilicon layer 76 adhered between adjacent spacer material 71-71 also becomes large, there are cases when a polysilicon layer 76 remains between spacer material 71-71 after etching, as well as instances when the polysilicon layer 11 of the foundation is not etched at all. As a result, even when the capacitor is formed using the processes shown in FIGS. 32 and 33, there are cases when current flows between the lower electrodes 76 and 11 of adjacent capacitors, and they do not function.
Therefore, in this case, it is necessary to make the distance between spacer material 71-71 sufficiently large and make sure that the adhered thickness of the polysilicon layer 76 between spacer material does not become large, causing the space between adjacent capacitors to become large, meaning that the demands for high densification and high integration of the memory cell cannot be satisfied.
Also, it can be seen that, during the etching of the polysilicon layer 76, burrs are readily generated on the remaining polysilicon layer 76.
In other words, when the polysilicon layer 76 is etched from the enlarged configuration shown in FIG. 36(A), as shown in FIG. 36(B), the polymer-like accumulated substance 79 generated by the reaction between the etching gas and the polysilicon is created on the inside edge (connecting sections between spacer material 71) of the top of polysilicon layer 76. Also, natural oxide film 80 has already been formed on the top edge of the outer surface of polysilicon 76, and this accumulated substance 79 and natural oxide film 80 are left as is, as burrs, without being etched.
If dielectric film 77 and polysilicon upper electrode 78 are formed with these kinds of burrs remaining, as shown in FIG. 36(C), stress is applied by the burr section, particularly to dielectric film 77, and pinholes are created in that film or localized film thinning (the portion shown by 81 in the figure) occurs. If these types of defects are present, insulation faults and a reduction of voltage resistance of the dielectric film occur, the charge cannot be normally accumulated as a capacitor for the memory cell, and there are instances when the memory cell does not function.
The purpose of our invention is to offer a semiconductor device and its manufacturing method that, along with making the film thickness of the electrode in the screen capacitor sufficiently uniform and fulfilling performance demands, increases the degree of integration, and has excellent reliability in conducting normal operations.